Paper Info
Title
Leakage energy reduction techniques in deep submicron cache memories: a comparative study
Abstract
Static energy consumption due to subthreshold leakage current is one of the main concern in on-chip level-1 and level-2 cache. In the last few years several techniques have been proposed to limit the subthreshold current in a SRAM cell. Unfortunately, these techniques also increase the dynamic energy during the cell access operation, with respect to the conventional SRAM architecture. In this paper the actual energy saving offered by low leakage approaches is investigated, within the context of a microprocessor memory hierarchy, taking into account their dynamic energy overheads. Simulation based on UMC 0.18mum-1.8V and ST 90nm-1V process models have been performed. Results show that, for both the technologies, the leakage energy saving achieved by the analyzed techniques in the first cache level turns out to be inadequate, owing to the extra dynamic energy dissipation. Only in UL2 they assure a net energy saving due to the smaller number of accesses
Year
DOI
Venue
2006
10.1109/ISCAS.2006.1693467
ISCAS
Keywords
Field
DocType
90 nm,1 v,deep submicron cache memories,microprocessor chips,leakage current,cache storage,leakage currents,sram chips,1.8 v,leakage energy reduction techniques,microprocessor memory hierarchy,sram architecture,0.18 micron,process model,power dissipation,computer science,energy dissipation,cache memory,chip,comparative study
Memory hierarchy,Leakage (electronics),Computer science,Dissipation,Cache,CPU cache,Static random-access memory,Electronic engineering,Subthreshold conduction,Energy consumption
Conference
ISSN
ISBN
Citations 
0271-4302
0-7803-9389-9
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Fabio Frustaci112917.55
Pasquale Corsonello227838.06
Stefania Perri326433.11
Giuseppe Cocorullo410617.00