Paper Info
Title
Cache conscious data layout organization for embedded multimedia applications
Abstract
Cache misses form a major bottleneck for real-time mul- timedia applications due to the off-chip accesses to the main memory. This results in both a major access bandwidth over- head (and related power consumption) as well as perfor- mance penalties. In this paper, we propose a new technique for organizing data in the main memory for data dominated multimedia applications so as to reduce majority of the con- flict cache misses. The focus of this paper is on the formal and heuristic algorithms we use to steer the data layout decisions and the experimental results obtained using a prototype tool. Experiments on real-life demonstrators illustrate that we are able to reduce upto % of the conflict misses for applications that are already aggressively transformed at the source-level. At the same time, we also reduce the off-chip data accesses by upto 78% and combined with address optimizations we are able to reduce the execution time. Thus our approach is com- plimentary to the more conventional way of reducing misses by reorganizing the execution order.
Year
DOI
Venue
2001
10.1145/367072.367849
DATE
Keywords
Field
DocType
cache conscious data layout,embedded multimedia application,data access,algorithm design and analysis,real time,data structures,chip,system level design,bandwidth,heuristic algorithm,embedded systems,prototypes
Bottleneck,Computer science,Cache,Real-time computing,Memory architecture,Data structure,Heuristic,Data layout,Parallel computing,Electronic system-level design and verification,Bandwidth (signal processing),Multimedia,Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-0993-2
20
1.92
References 
Authors
7
5
Name
Order
Citations
PageRank
C. Kulkarni125513.15
C. Ghez2433.76
M. Miranda314411.00
F. Catthoor489783.95
H. De Man549083.62