Name
Abstract | ||
|---|---|---|
Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/MDT.2007.111 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
leakage power,input pattern generation,nanometer cmos circuit,gate-tunneling,nanometer cmos,input pattern,leakage minimization technique,proposed macromodel,leakage current,power dissipation,leakage currents,low-power digital circuit design,new heuristic approach,low-power electronics,reverse-biased junction band-to-band-tunneling leakage current,individual cell,nanoscale cmos vlsi,new macromodeling technique,vlsi,integrated circuit design,nanoscale cmos vlsi circuit,gate-tunneling current,cmos digital integrated circuits,leakage power minimization technique,supply-threshold voltage scaling,subthreshold leakage current,fan-out effect,nanoelectronics,cell characterization,logic gates,low power electronics,transistors,cmos integrated circuits,cmos technology,tunneling | Nanoelectronics,Digital electronics,Logic gate,Leakage (electronics),Computer science,Electronic engineering,CMOS,Subthreshold conduction,Transistor,Low-power electronics | Journal |
Volume | Issue | ISSN |
24 | 4 | 0740-7475 |
Citations | PageRank | References |
2 | 0.51 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyung Ki Kim | 1 | 99 | 21.62 |
| Yong-bin Kim | 2 | 338 | 55.72 |
| Minsu Choi | 3 | 156 | 27.63 |
| Nohpill Park | 4 | 72 | 17.90 |