Paper Info
Title
An area efficient low power high speed S-Box implementation using power-gated PLA
Abstract
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-Box), which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. This paper presents a low power design of Rijndael S-Box for the SubByte transformation using power-gating and PLA design techniques to reduce area and leakage power during stand-by mode. The proposed design is implemented using 110nm standard CMOS process with 1.2V power supply. The proposed design reduces the total leakage power and the total transistor count to 10% and 50% of the conventional design, respectively while improving the speed performance by ten times.
Year
DOI
Venue
2014
10.1145/2591513.2591575
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
vlsi,aes,logic arrays,s-box,pla,gate arrays,power gate,s box
Symmetric-key algorithm,Transistor count,S-box,Hardware complexity,Advanced Encryption Standard,Computer science,Leakage power,Real-time computing,Electronic engineering,Cmos process,Embedded system
Conference
ISSN
Citations 
PageRank 
1066-1395
0
0.34
References 
Authors
3
2
Name
Order
Citations
PageRank
Ho Joon Lee1134.08
Yong-bin Kim233855.72