Name
Abstract | ||
|---|---|---|
We present a hardware implementation of an efficient image compression method optimised for small FPGAs. The compression method is based on a codebook of reference patterns to support multiplication-free quantisation of the image data. Based on specific features of a low-cost FPGA architecture, a pipelined implementation is developed and evaluated. The implemented hardware benefits from the simple structure of the compression method and is optimised for area and performance. The realised hardware as well as the underlying compression mechanism are described and the synthesis results for different model variants are compared. The results show that a high compression rate is possible at extremely low hardware costs. Also, a high frame rate can be obtained even on a low-cost FPGA. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/FPT.2008.4762415 | Taipei |
Keywords | Field | DocType |
data compression,field programmable gate arrays,image coding,pipeline processing,quantisation (signal),codebook-based image compression method,field programmable gate array,hardware implementation,multiplication-free quantisation,pipelined implementation | Data compression ratio,Computer science,Parallel computing,Field-programmable gate array,Hamming distance,Frame rate,Pixel,Computer hardware,Data compression,Image compression,Embedded system,Codebook | Conference |
ISBN | Citations | PageRank |
978-1-4244-2796-3 | 0 | 0.34 |
References | Authors | |
1 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peter Zipf | 1 | 186 | 45.00 |
| Heiko Hinkelmann | 2 | 54 | 11.69 |
| Hui Shao | 3 | 0 | 0.34 |
| Radu Dogaru | 4 | 71 | 18.23 |
| Manfred Glesner | 5 | 1121 | 255.04 |