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YOUNG-JUNG CHOI
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Name
Affiliation
Papers
YOUNG-JUNG CHOI
Hynix Semicond. Inc., Kyoungki-do
17
Collaborators
Citations
PageRank
75
63
9.75
Referers
Referees
References
251
293
60
Search Limit
100
293
Publications (17 rows)
Collaborators (75 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface
3
0.60
2013
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface
2
0.37
2012
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology
1
0.39
2012
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces
13
0.93
2012
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology
1
0.35
2011
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface
0
0.34
2010
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster.
0
0.34
2010
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application
1
0.36
2009
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
1
0.40
2009
A Fast-Lock Synchronous Multi-Phase Clock Generator Based On A Time-To-Digital Converter
2
0.44
2009
Coverage Expandable Current Type Code Controlled Dcc With Tdc-Based Range Selector
0
0.34
2009
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
9
0.94
2008
A 0.17–1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme
3
0.47
2008
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.
5
0.65
2008
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL
5
0.83
2007
A One-Cycle Lock Time Slew-Rate-Controlled Output Driver.
13
1.24
2007
Sonar Localization Using Ubiquitous Sensor Network For Water Pollution Monitoring Fish Robots
4
0.77
2007
1