Title
Fabrication Of A Magnetic Tunnel Junction-Based 240-Tile Nonvolatile Field-Programmable Gate Array Chip Skipping Wasted Write Operations For Greedy Power-Reduced Logic Applications
Abstract
A nonvolatile field-programmable gate array (NVFPGA) test chip with 240 tiles (the basic components) in a 12 x 20 2D-array is fabricated by 90 nm CMOS and 70 nm magnetic tunnel junction (MTJ) technologies. Since not only circuit configuration data but also temporal data are still remained in the MTJ devices even when the power supply is cut off, standby power dissipation is completely eliminated by utilizing tile-level power gating. Power reduction is further accelerated by skipping wasted write operations of nonvolatile flip-flops (NVFFs) for storing temporal data when the temporal data and the stored one are the same. As a typical application, a motion-vector prediction function is implemented on the proposed NVFPGA, which results in a write power reduction of 77% compared to that of a conventional MTJ-based NVFPGA and a total power reduction of 70% compared to that of an SRAM-based FPGA.
Year
DOI
Venue
2013
10.1587/elex.10.20130772
IEICE ELECTRONICS EXPRESS
Keywords
Field
DocType
field-programmable gate array, magnetic tunnel junction device, nonvolatile logic-in-memory architecture, power-gating
Computer science,Programmable logic array,Field-programmable gate array,Electronic engineering,Power gating,Gate array,Tunnel magnetoresistance,Computer hardware,Electrical engineering,Fabrication,Programmable logic device,Macrocell array
Journal
Volume
Issue
ISSN
10
23
1349-2543
Citations 
PageRank 
References 
9
1.06
0
Authors
11
Name
Order
Citations
PageRank
Daisuke Suzuki1477.32
Masanori Natsui28015.10
Akira Mochizuki3344.24
Sadahiko Miura4797.86
Hiroaki Honjo59011.43
Keizo Kinoshita6335.05
Hideo Sato791.06
Shoji Ikeda8141.58
Tetsuo Endoh915535.26
Hideo Ohno1012333.57
Takahiro Hanyu1144178.58