Title
Impulse: Building a Smarter Memory Controller
Abstract
Impulse is a new memory system architecture that adds two important features to a traditional memory controller First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller which can hide much of the latency of DRAM accesses.In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system carl be used to improve the performance of memory-bound programs. For the NAS conjugate gradient benchmark, Impulse improves performance by 67%. Because it requires no modification to processor; cache, or bus designs, Impulse can be adopted in conventional systems. In addition to scientific applications, we expect that Impulse will benefit regularly strided, memory-bound applications of commercial importance, such as database and multimedia programs.
Year
DOI
Venue
1999
10.1109/HPCA.1999.744334
HPCA
Keywords
Field
DocType
performance,bandwidth,databases,processor design,sparse matrices,database management systems,computer science,conjugate gradient,data access,memory controller
Registered memory,Interleaved memory,Physical address,Computer science,Parallel computing,Cache-only memory architecture,Real-time computing,Memory map,Memory address,Computer hardware,Memory controller,Memory architecture
Conference
ISBN
Citations 
PageRank 
0-7695-0004-8
126
7.78
References 
Authors
15
12
Search Limit
100126
Name
Order
Citations
PageRank
John B. Carter11785162.82
Wilson C. Hsieh22532261.94
Leigh Stoller346249.03
Mark R. Swanson418614.34
Lixin Zhang557145.96
Erik Brunvand650966.09
Al Davis798654.47
Chen-Chi Kuo814710.96
Ravindra Kuramkote915414.86
Michael A. Parker101267.78
Lambert Schaelicke1127920.23
Terry Tateyama121267.78