Title
A statistical model of logic gates for Monte Carlo simulation including on-chip variations
Abstract
Process variations are becoming a paramount design problem in nano-scale VLSI. We present a framework for the statistical model of logic gates that describes both inter-die and intra-die variations of performance parameters such as propagation delay and leakage currents. This allows fast but accurate behavioral-level Monte-Carlo simulations, that could be useful for full-custom digital design optimization and yield prediction, and enables the development of a yield-aware digital design flow. The model can incorporate correlation between mismatch parameters and dependence on distance and position, and can be extracted by fitting of Monte-Carlo transistor level simulations. An example implementation using Verilog-A hardware description language in Cadence environment is presented.
Year
DOI
Venue
2007
10.1007/978-3-540-74442-9_50
PATMOS
Keywords
Field
DocType
monte carlo simulation,cadence environment,accurate behavioral-level monte-carlo simulation,yield-aware digital design flow,logic gate,paramount design problem,example implementation,statistical model,full-custom digital design optimization,intra-die variation,verilog-a hardware description language,monte-carlo transistor level simulation,on-chip variation,propagation delay,chip,hardware description language,digital design,process variation,leakage current,monte carlo
Monte Carlo method,Logic gate,Propagation delay,Computer science,Electronic engineering,Design flow,Logic simulation,Statistical model,Very-large-scale integration,Hardware description language
Conference
Volume
ISSN
ISBN
4644
0302-9743
3-540-74441-X
Citations 
PageRank 
References 
1
0.38
13
Authors
5
Name
Order
Citations
PageRank
Francesco Centurelli15615.93
luca giancane21238.15
Mauro Olivieri338536.09
giuseppe scotti430839.14
A. Trifiletti543363.29