Paper Info
Title
A scalable reconfiguration mechanism for fast dynamic reconfiguration
Abstract
Hardware reconfiguration during run-time provides attractive features like fast adaptivity, high hardware utilisation, and low area consumption due to efficient reuse of hardware components. In this paper, a novel multi-layered reconfiguration mechanism is proposed that allows frequent dynamic reconfiguration at very low latencies. It combines successful existing techniques such as multi-context and partial reconfiguration with new ideas like tag-matching and reconfiguration profiles to one uniform approach. As an important feature, the proposed reconfiguration mechanism is well scalable and can be adapted to given hardware structures easily, thus being applicable to virtually any reconfigurable fabric. In contrast to many existing techniques, it also supports even very heterogeneous architectures found for instance in custom reconfigurable systems. By experimental results, we show that our reconfiguration mechanism provides significantly lower reconfiguration latencies compared to some common existing techniques.
Year
DOI
Venue
2008
10.1109/FPT.2008.4762377
FPT
Keywords
Field
DocType
heterogeneous architectures,reconfiguration profiles,reconfigurable architectures,hardware structures,hardware components reuse,tag-matching,scalable reconfiguration mechanism,fast dynamic reconfiguration,hardware reconfiguration,field programmable gate arrays,multilayered reconfiguration mechanism,low latency,hardware,switches,computer architecture,probability density function,data mining,redundancy,registers
Reuse,Computer science,Parallel computing,Field-programmable gate array,Hardware reconfiguration,Real-time computing,Redundancy (engineering),Control reconfiguration,Embedded system,Scalability
Conference
ISBN
Citations 
PageRank 
978-1-4244-2796-3
3
0.52
References 
Authors
11
3
Name
Order
Citations
PageRank
Heiko Hinkelmann15411.69
Peter Zipf218645.00
Manfred Glesner31121255.04