Title
Network-on-Chip multicasting with low latency path setup
Abstract
A low-latency path setup approach with multiple setup packets for parallel set is presented. It reduces the header overhead compared to multiaddress encoding. Further, we propose four variants of deadlock-free multicast routing algorithms using different subpath generation methods, different destination partitioning, and channel sharing strategies. Experimental results show that the quatuor partitions path-like tree outperforms other algorithms.
Year
DOI
Venue
2011
10.1109/VLSISoC.2011.6081594
VLSI-SOC
Keywords
Field
DocType
multiple setup packets,subpath generation methods,deadlock free multicast routing algorithms,low latency path setup,channel sharing strategies,multiaddress encoding,network on chip multicasting,routing protocols,quatuor partitions,destination partitioning,header overhead,multicast protocols,parallel set,network-on-chip,optimization,network on chip,encoding,unicast,routing,payloads
Protocol Independent Multicast,Link-state routing protocol,Computer science,Computer network,Network on a chip,Header,Multicast,Latency (engineering),Distance Vector Multicast Routing Protocol,Routing protocol
Conference
Volume
Issue
ISBN
null
null
978-1-4577-0169-6
Citations 
PageRank 
References 
2
0.39
13
Authors
6
Name
Order
Citations
PageRank
Wenmin Hu1253.11
Zhonghai Lu21063100.12
Axel Jantsch31875169.83
Hengzhu Liu48623.28
Botao Zhang55510.73
Dongpei Liu6193.60