Name
Title | ||
|---|---|---|
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface |
Abstract | ||
|---|---|---|
DRAM speed already reaches 7Gb/s/pin for GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the self-generated internal noise of DRAM increases due to low efficiency of the internal voltage generator, especially the VPP voltage generator [2]. In general, the sensitivity of PLL to supply noise gives rise to large jitter accumulation. If the supply noise frequency is close to the PLL bandwidth, more jitter peaking occurs. Therefore, the PLL bandwidth is an important parameter to achieve low jitter performance [3]. Crosstalk becomes a crucial issue for over 7Gb/s GDDR interface [1]. However, the complexity of the transmitter and the CIO, capacitance of I/O, increase due to additional equalizers and pre- and de-emphasis drivers. For a compact transmitter, a low-overhead boosted transmitter is developed [4]. This paper presents an adaptive-bandwidth PLL in response to the supply and channel noises, a fast pre-charged data sampler without an additional decision-feedback equalizer (DFE), a crosstalk-induced-jitter-reduction technique and a compact transmitter with pre- and de-emphasis. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISSCC.2013.6487749 | ISSCC |
Keywords | Field | DocType |
noise interference,dfe less fast precharge sampling,adaptive bandwidth pll,jitter performance,jitter peaking,internal voltage generator,self generated internal noise,gddr interface,dram chips,supply noise frequency,crosstalk,bit rate,phase locked loops,crosstalk induced jitter reduction,compact transmitter,data sampling margin,jitter accumulation,boosted transmitter,deemphasis,interference suppression,dram speed,decision feedback equalizer,graphics dram interface,pll bandwidth,intersymbol interference,preemphasis | Dram,Transmitter,Phase-locked loop,Intersymbol interference,Computer science,Communication channel,Electronic engineering,Bandwidth (signal processing),Interference (wave propagation),Jitter,Electrical engineering | Conference |
Volume | ISSN | ISBN |
56 | 0193-6530 | 978-1-4673-4515-6 |
Citations | PageRank | References |
3 | 0.60 | 3 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Junyoung Song | 1 | 40 | 11.42 |
| Hyun-Woo Lee | 2 | 162 | 43.02 |
| Soo-Bin Lim | 3 | 6 | 1.33 |
| Sewook Hwang | 4 | 41 | 10.43 |
| Yunsaing Kim | 5 | 39 | 5.45 |
| Young-Jung Choi | 6 | 63 | 9.75 |
| Byongtae Chung | 7 | 76 | 7.44 |
| Chulwoo Kim | 8 | 9 | 4.86 |