Name
Abstract | ||
|---|---|---|
This paper proposes a design approach targeting circuits operating at extremely low supply voltages, with the goal of reducing the voltage at which energy is minimized, thereby improving the achievable energy efficiency of the circuit. The proposed methods accomplish this by minimizing the circuit's ratio of leakage to active current. The first method, super pipelining, increases the number of pipeline stages compared to conventional ultra low voltage (ULV) pipelining strategies, reducing the leakage/dynamic energy ratio and simultaneously improving performance and energy efficiency. Measurements of super-pipelined multipliers demonstrate 30% energy savings and 1.6× performance improvement. Since super pipelining reduces the logic depth between registers, two-phase latch based design is employed to compensate for reduced averaging effects and provide better variation tolerance. The second technique introduces a parallel-pipelined architecture that suppresses leakage energy by ensuring full utilization of functional units and reduces memory size. We apply these techniques to a 16-b 1024-pt complex-valued Fast Fourier Transform (FFT) core along with low-power first-in first-out (FIFO) design and robust clock distribution network. The FFT core is fabricated in 65 nm CMOS and consumes 15.8 nJ/FFT with a clock frequency of 30 MHz and throughput of 240 Msamples/s at Vdd=270 mV, providing 2.4× better energy efficiency than current state-of-art and >; 10× higher throughput than typical ULV designs. Measurements of 60 dies show modest frequency (energy) σ/μ spreads of 7% (2%). |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/JSSC.2011.2169311 | IEEE Journal of Solid-state Circuits |
Keywords | Field | DocType |
parallel-pipelined architecture,subthreshold cmos circuits,leakage current,leakage-dynamic energy ratio,leakage currents,super-pipelined energy efficient subthreshold fft core,size 65 nm,low-power fifo design,complex-valued fft core,two-phase latch based design,cmos technology,ulv pipelining strategy,super-pipelined multiplier,robust clock distribution network,cmos digital integrated circuits,low-power first-in first-out design,flip-flops,clock distribution networks,frequency 30 mhz,ultra low voltage (ulv) design,ultra low voltage pipelining strategy,voltage 270 mv,energy efficiency,fast fourier transform (fft),fast fourier transforms,complex-valued fast fourier transform core,super-pipelining,functional unit,switches,fast fourier transform,first in first out,computer architecture,energy efficient,registers | Pipeline (computing),Leakage (electronics),Efficient energy use,Computer science,CMOS,Electronic engineering,Fast Fourier transform,Low voltage,Subthreshold conduction,Clock rate | Journal |
Volume | Issue | ISSN |
47 | 1 | 0018-9200 |
Citations | PageRank | References |
24 | 1.41 | 16 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dongsuk Jeon | 1 | 183 | 21.01 |
| Mingoo Seok | 2 | 601 | 80.71 |
| Chaitali Chakrabarti | 3 | 1978 | 184.17 |
| David Blaauw | 4 | 8916 | 823.47 |
| Dennis Sylvester | 5 | 5295 | 535.53 |