Name
Abstract | ||
|---|---|---|
A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter cir... |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/4.509863 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Niobium,Adders,Compressors,Delay,Frequency estimation,Integrated circuit interconnections,Binary trees,Multiplexing,CMOS technology,Voltage | Journal | 31 |
Issue | ISSN | Citations |
6 | 0018-9200 | 34 |
PageRank | References | Authors |
4.26 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroshi Makino | 1 | 172 | 30.23 |
| Y. Nakase | 2 | 34 | 4.26 |
| H. Suzuki | 3 | 238 | 31.31 |
| H. Morinaka | 4 | 38 | 5.36 |
| Hirofumi Shinohara | 5 | 141 | 25.79 |
| K. Mashiko | 6 | 49 | 9.50 |