Paper Info
Title
A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule
Abstract
We propose a yield improvement methodology which repairs a faulty chip due to logic defect by using a repairable scan flip-flop (R-SFF). Our methodology improves area penalty, which is a large issue for logic repair technology in actual products, by using repair grouping and a redundant cell insertion algorithm and by pushing the design rule for the repairable area of R-SFF. Additionally, compared with the conventional method, we reduce the number of wire connections around redundant cells by improving the replacement method of the faulty cell by the redundant cell. The proposed methodology reduces the total area penalty caused by the logic redundant repair to 3.6% and improves the yield, that is the number of good chips on a wafer, by 4.7% when the defect density is 1.0[1/cm^2]. Furthermore, we propose the strategy to repair the in-field failures due to latent defect for the chip whose repair function had not been used in the shipment test.
Year
DOI
Venue
2012
10.1145/2159542.2159549
ACM Trans. Design Autom. Electr. Syst.
Keywords
Field
DocType
push rule,reliability improvement methodology,redundant cell,area penalty,defect density,logic repair technology,latent defect,repair function,redundant cell insertion algorithm,repairable scan flip-flop,repair grouping,logic redundant repair,faulty cell,chip,design rules,logic redundancy,opc,yield
Critical area analysis,Computer science,Parallel computing,Chip,Flip-flop,Reliability engineering,Logic redundancy
Journal
Volume
Issue
ISSN
17
2
1084-4309
Citations 
PageRank 
References 
2
0.37
11
Authors
6
Name
Order
Citations
PageRank
Masanori Kurimoto1162.82
Jun Matsushima2134.09
Shigeki Ohbayashi3488.88
Yoshiaki Fukui4231.24
Michio Komoda520.37
Nobuhiro Tsuda660.86