Name
Title | ||
|---|---|---|
3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS |
Abstract | ||
|---|---|---|
ADC-based receivers are currently being proposed in high-speed serial link applications to enable flexible, complex, and robust digital equalization in order to support operation over high loss channels [1-3]. However, the power dissipation of the ADC, as well as the digital equalization that follows, is a major concern for wireline receiver applications [3]. In this work, a hybrid ADC-based receiver architecture is presented that introduces innovations in both the ADC and the digital equalizer design. First, an analog 3-tap feed-forward equalizer (FFE) is efficiently embedded into a 6b time-interleaved SAR ADC, allowing for reductions in both ADC resolution and digital equalizer complexity. Second, significant power reduction is achieved by detecting reliable symbols at the ADC output and dynamically enabling/disabling the digital equalizer. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISSCC.2015.7062926 | ISSCC |
Keywords | Field | DocType |
attenuation,bit error rate | Serial communication,Wireline,Equalization (audio),Computer science,Dissipation,Communication channel,CMOS,Electronic engineering,Successive approximation ADC,Bit error rate | Conference |
Citations | PageRank | References |
2 | 0.43 | 4 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayman Shafik | 1 | 71 | 9.73 |
| Ehsan Zhian Tabasy | 2 | 43 | 6.20 |
| Shengchang Cai | 3 | 20 | 5.28 |
| Keytaek Lee | 4 | 11 | 2.46 |
| Sebastian Hoyos | 5 | 234 | 29.24 |
| Samuel Palermo | 6 | 142 | 22.07 |