| Automated Tuning for Silicon Photonic Filters | 0 | 0.34 | 2022 |
| A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS | 2 | 0.51 | 2020 |
| A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques | 0 | 0.34 | 2020 |
| A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS | 0 | 0.34 | 2019 |
| A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS | 2 | 0.37 | 2019 |
| A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE | 1 | 0.48 | 2018 |
| A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS. | 1 | 0.36 | 2017 |
| CMOS ADC-based receivers for high-speed electrical and optical links. | 2 | 0.50 | 2016 |
| A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization. | 6 | 0.79 | 2016 |
| 3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS | 2 | 0.43 | 2015 |
| Adaptively-tunable RF photonic filters | 0 | 0.34 | 2015 |
| A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS | 4 | 0.50 | 2015 |
