Name
Abstract | ||
|---|---|---|
As CMOS technology is scaled down more aggressively; the reliability mechanism (or aging effect) caused by progressive gate oxide breakdown (also called time dependent dielectric breakdown (TDDB)) has become a major reliability concern. The oxide breakdown is categorized into hard breakdown (HBD) and soft breakdown (SBD). With the present of HBD and SBD, it is difficult to control the ON current of the MOSFET device. Especially, HBD causes a catastrophic failure of the device and the entire circuits. In this paper, the TDDB effects on the delay and power of the nanoscale CMOS circuits are analyzed using ISCAS85 benchmark circuits, which are designed using a 45-nm CMOS predictive technology model. Based on the TDDB analysis, a new hard breakdown monitoring circuit has been proposed. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/MWSCAS.2012.6292050 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
resistors,logic gates,cmos integrated circuits,failure analysis | Logic gate,Dielectric strength,Computer science,Time-dependent gate oxide breakdown,CMOS,Electronic engineering,Resistor,Gate oxide,MOSFET,Electronic circuit | Conference |
ISSN | Citations | PageRank |
1548-3746 | 1 | 0.36 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ho Joon Lee | 1 | 13 | 4.08 |
| Yong-bin Kim | 2 | 338 | 55.72 |
| Kyung Ki Kim | 3 | 99 | 21.62 |