Name
Abstract | ||
|---|---|---|
A 25GS/s 8-way time-interleaved binary search ADC employs a novel soft-decision selection algorithm to improve metastability tolerance and relax T/H settling requirements. The T/H design is further relaxed with reduced loading from a new shared-input three comparator structure. Fabricated in GP 65nm CMOS, the ADC achieves 4.62-bits ENOB at Nyquist and 143 fJ/conv.-step FOM, while consuming 88mW and occupying 0.24mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
core ADC area. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/VLSIC.2015.7231248 | 2015 Symposium on VLSI Circuits (VLSI Circuits) |
Keywords | Field | DocType |
ADC,binary search,soft-decision selection,time interleaving | Comparator,Computer science,Selection algorithm,Effective number of bits,Electronic engineering,CMOS,Successive approximation ADC,Nyquist–Shannon sampling theorem,Binary search algorithm,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
2158-5601 | 978-4-86348-502-0 | 4 |
PageRank | References | Authors |
0.50 | 4 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shengchang Cai | 1 | 20 | 5.28 |
| Ehsan Zhian Tabasy | 2 | 43 | 6.20 |
| Ayman Shafik | 3 | 71 | 9.73 |
| Shiva Kiran | 4 | 12 | 2.71 |
| Sebastian Hoyos | 5 | 234 | 29.24 |
| Samuel Palermo | 6 | 142 | 22.07 |