Name
Abstract | ||
|---|---|---|
CMOS ADC-based serial link receivers enable powerful digital equalization and symbol detection techniques for high data rate operation over electrical and optical wireline channels. Common ADC architectures and equalization techniques that allow 10 Gb/s and higher operation are surveyed in this article. As time-interleaving is most often employed to achieve these high sampling rates, the associated errors and calibration techniques are presented. The impact of ADC quantization noise on receiver performance and how this can be improved via embedded partial analog equalization are detailed. A description of a 65 nm CMOS hybrid ADC-based receiver architecture that employs a 3-tap analog FFE embedded inside a 6-bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer operating at 10 Gb/s concludes the discussion. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/MCOM.2016.7588288 | IEEE Communications Magazine |
Keywords | Field | DocType |
Receivers,Calibration,Integrated circuits,Digital signal processing,Bandwidth,Optical fiber communication,CMOS technology | Serial communication,Digital signal processing,Telecommunications,Equalization (audio),Computer science,Computer network,Electronic engineering,CMOS,Bandwidth (signal processing),Successive approximation ADC,Quantization (signal processing),Integrated circuit | Journal |
Volume | Issue | ISSN |
54 | 10 | 0163-6804 |
Citations | PageRank | References |
2 | 0.50 | 11 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Samuel Palermo | 1 | 142 | 22.07 |
| Sebastian Hoyos | 2 | 234 | 29.24 |
| Ayman Shafik | 3 | 71 | 9.73 |
| Ehsan Zhian Tabasy | 4 | 43 | 6.20 |
| Shengchang Cai | 5 | 20 | 5.28 |
| Shiva Kiran | 6 | 12 | 2.71 |
| Keytaek Lee | 7 | 11 | 2.46 |