Name
Title | ||
|---|---|---|
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. |
Abstract | ||
|---|---|---|
The implementation of a digital four-level pulse-amplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Implemented in an experimental chip fabricated in 14nm CMOS, the VD is designed to recover data at 25.6 Gb/s over an emulated time-dispersive channel. The power consumption of the VD together with the test circuitry is 105mW at a supply of 0.7V, achieving an overall energy efficiency of 4.1 pJ/b. At a supply of 0.8V, a data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b. The VD occupies an area of 0.507 +/- 0.717mm(2). Experimental results showing system performance are obtained using a (2(15)-1)-bit pseudo-random binary sequence. The impact on the bit error rate of the synchronization length for block initialization is also measured. |
Year | Venue | Field |
|---|---|---|
2016 | Proceedings of the European Solid-State Circuits Conference | Synchronization,Computer science,Pseudorandom binary sequence,Communication channel,CMOS,Electronic engineering,Chip,Modulation,Detector,Bit error rate |
DocType | ISSN | Citations |
Conference | 1930-8833 | 0 |
PageRank | References | Authors |
0.34 | 4 | 13 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hazar Yueksel | 1 | 7 | 4.15 |
| Matthias Braendli | 2 | 158 | 24.28 |
| A. Burg | 3 | 1426 | 126.54 |
| Giovanni Cherubini | 4 | 52 | 9.18 |
| Roy D. Cideciyan | 5 | 19 | 3.71 |
| Pier Andrea Francese | 6 | 138 | 25.33 |
| Simeon Furrer | 7 | 0 | 1.69 |
| Marcel A. Kossel | 8 | 179 | 33.86 |
| Lukas Kull | 9 | 141 | 18.63 |
| Danny Luu | 10 | 16 | 7.55 |
| Christian Menolfi | 11 | 245 | 41.54 |
| Thomas Morf | 12 | 244 | 42.54 |
| Thomas Toifl | 13 | 275 | 48.02 |