Paper Info
Title
Determination of safe reliability region over temperature and current density for through wafer vias.
Abstract
Circular and slot backside vias are stressed over current and temperature and the resulting failure times are fitted to Black's equation. Contour plots of the FIT rate are generated and the reliability of circular and slot vias are compared. It is demonstrated that in most cases the FIT rate of the circular via is statistically significantly lower than that of the slot via. However, both types are easily able to meet a goal of 100 FITs in 10years at T=125°C and J=0.25×106A/cm2. The contour map of the FIT rate defines the region where the via can operate reliably. By use of the 95% upper confidence bound, the region of safe operation is reduced in size, adding a layer of margin to the prediction of via reliability. The approach described here provides a “reliability map” for designers allowing trade-offs between temperature current to be made when designing for high reliability.
Year
DOI
Venue
2017
10.1016/j.microrel.2016.09.011
Microelectronics Reliability
Keywords
Field
DocType
Through-wafer via,Backside via,Black's equation,Likelihood ratio,FIT rate
Current density,Wafer,Overcurrent,Contour line,Electronic engineering,Black's equation,Engineering
Journal
Volume
ISSN
Citations 
68
0026-2714
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Charles S. Whitman185.83
Michael Meeder221.93
P. J. Zampardi300.68