Name
Title | ||
|---|---|---|
Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation |
Abstract | ||
|---|---|---|
In this work, to increase the timing yield of Tunnel Field Effect Transistor (TFET) circuits in the presence of the process variation, we propose to use MOSFET-based gates instead of some TFET-based gates in the TFET circuits. This hybridization approach originates from the fact that TFETs are more sensitive to process variation, when compared to conventional MOSFETs. First, we investigate the impact of process variations on Homojunction InAs TFETs by extracting the distributions of electrical parameters such as threshold voltage. Then, a hybrid TFET-MOSFET circuit design approach for increasing the reliability of the TFET circuits is introduced. The power consumptions of hybrid circuits are considerably smaller than the corresponding ones realized using CMOS circuits. In the proposed hybrid approach, the circuit is basically implemented in TFET to reduce the power and energy consumption while the gates whose their variations may lead to the timing violation, are implemented using MOSFET-based gates. The decision on replacing the TFET-based gates by their corresponding MOSFET-based gates during the hybrid design is made through a heuristic algorithm. The proposed algorithm considers the sensitivity of each TFET-based gate to the process variation. To assess the efficacy of the proposed approach, the proposed algorithm is applied to some circuits of the ISCAS'85 and ISCAS'89 benchmark packages. The results show that the reliability of the TFET-MOSFET-based circuits are up to 74% larger than that of the pure TFET-based circuits. Furthermore, the energy and leakage power consumptions of the proposed hybrid circuits are up to 56% and 80%, respectively, smaller than those of the pure MOSFET-based design. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/VLSI-SoC.2016.7753578 | 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Keywords | Field | DocType |
Hybrid TFET-MOSFET design,Tunnel FET,Reliability,Process variation,Low power design | Tunnel field-effect transistor,Logic gate,Semiconductor device modeling,Circuit design,CMOS,Electronic engineering,Process variation,Engineering,Electronic circuit,MOSFET,Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-5090-3562-5 | 1 | 0.35 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maede Hemmat | 1 | 1 | 0.35 |
| Mehdi Kamal | 2 | 189 | 30.41 |
| Ali Afzali-kusha | 3 | 365 | 54.65 |
| Massoud Pedram | 4 | 7801 | 1211.32 |