Name
Abstract | ||
|---|---|---|
For monolithic heterogeneous integration, fast yet low-power processing and storage. and high integration density, the objective of the EU GREAT project is to co-integrate multiple digital and analog functions together within CMOS by adapting the Magnetic Tunneling Junctions (MTJs) into a single baseline technology enabling logic, memory, and analog functions. particularly for Internet of Things (IoT) platforms. This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). This paper presents the progress in the project from the technology, compact modeling, process design kit, standard cells, as well as memory and system level design evaluation and exploration. The proposed technology and toolsets are giant leaps towards heterogeneous integrated technology and architectures for IoT. |
Year | Venue | Field |
|---|---|---|
2018 | PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | Computer architecture,Computer science,Electronic system-level design and verification,Internet of Things,Spintronics,CMOS,Real-time computing,Memory management,Process design,LEAPS |
DocType | ISSN | Citations |
Conference | 1530-1591 | 1 |
PageRank | References | Authors |
0.35 | 0 | 18 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mehdi B. Tahoori | 1 | 1537 | 163.44 |
| Sarath Mohanachandran Nair | 2 | 17 | 5.91 |
| Rajendra Bishnoi | 3 | 132 | 19.64 |
| Sophiane Senni | 4 | 22 | 6.06 |
| Jad Mohdad | 5 | 2 | 0.75 |
| Frédérick Mailly | 6 | 25 | 11.37 |
| Lionel Torres | 7 | 346 | 53.92 |
| Pascal Benoit | 8 | 262 | 29.52 |
| Abdoulaye Gamatié | 9 | 251 | 30.18 |
| Pascal Nouet | 10 | 31 | 14.07 |
| F. Ouattara | 11 | 1 | 0.35 |
| Gilles Sassatelli | 12 | 583 | 83.50 |
| Kotb Jabeur | 13 | 33 | 7.43 |
| Pierre Vanhauwaert | 14 | 117 | 8.40 |
| A. Atitoaie | 15 | 1 | 0.35 |
| I. Firastrau | 16 | 1 | 0.35 |
| Gregory Di Pendina | 17 | 33 | 7.27 |
| Guillaume Prenat | 18 | 80 | 13.62 |