Name
Title | ||
|---|---|---|
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. |
Abstract | ||
|---|---|---|
Rapidly emerging workloads require rapidly developed chips. The Celerity 16-nm open-source SoC was implemented in nine months using an architectural trifecta to minimize development time: a general-purpose tier comprised of open-source Linux-capable RISC-V cores, a massively parallel tier comprised of a RISC-V tiled manycore array that can be scaled to arbitrary sizes, and a specialization tier th... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/MM.2018.022071133 | IEEE Micro |
Keywords | Field | DocType |
Memory management,Programming,Open source software,Energy efficiency,System-on-chip,Reduced instruction set computing | RISC-V,Programming paradigm,Massively parallel,Efficient energy use,Computer science,Parallel computing,Global address space,Open source software | Journal |
Volume | Issue | ISSN |
38 | 2 | 0272-1732 |
Citations | PageRank | References |
9 | 0.59 | 0 |
Authors | ||
20 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Scott Davidson | 1 | 14 | 3.05 |
| Shaolin Xie | 2 | 9 | 0.59 |
| Christopher Torng | 3 | 33 | 3.43 |
| Khalid Al-Hawai | 4 | 9 | 0.59 |
| Austin Rovinski | 5 | 137 | 7.24 |
| Tutu Ajayi | 6 | 20 | 3.28 |
| Luis Vega | 7 | 18 | 2.52 |
| Chun Zhao | 8 | 27 | 7.67 |
| Ritchie Zhao | 9 | 134 | 8.19 |
| Steve Dai | 10 | 104 | 10.71 |
| Aporva Amarnath | 11 | 39 | 5.18 |
| Bandhav Veluri | 12 | 14 | 1.36 |
| Paul Gao | 13 | 16 | 2.41 |
| Anuj Rao | 14 | 9 | 0.59 |
| Gai Liu | 15 | 57 | 6.11 |
| Rajesh K. Gupta | 16 | 4570 | 390.84 |
| Zhiru Zhang | 17 | 1020 | 71.74 |
| Ronald G. Dreslinski | 18 | 1258 | 81.02 |
| Christopher Batten | 19 | 478 | 34.23 |
| Michael Bedford Taylor | 20 | 1707 | 154.51 |