Name
Abstract | ||
|---|---|---|
The availability and efficiency of reliability simulators for analog ICs is becoming critical with the scaling of devices down to the nanometer nodes. Two of the main challenges here are how to simultaneously include different sources of unreliability (such as the time-zero or spatial variability and the aging or time-dependent variability), and how to account for the self-induced changes in device biasing (i.e., stress conditions) caused by the device wear-out. In addition to the already existing stochastic models for time-zero variability, new models for the stochastically-distributed aging mechanisms have been developed in recent years. The combination of these challenges with the need for dealing with a stochastic model for aging, causes a serious computational load issue. This paper presents different methods to accurately include reliability in the simulation of analog ICs while preventing the simulation to become unaffordable in terms of CPU time and load. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/SMACD.2017.7981618 | 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) |
Keywords | Field | DocType |
reliability simulation,transistor aging,BTI,HCI,stress,process variability,time-dependent variability,CPU load | Stress conditions,CPU time,Flow (psychology),Stochastic modelling,Spatial variability,Engineering,Transient analysis,Scaling,Reliability engineering | Conference |
ISSN | ISBN | Citations |
2575-4874 | 978-1-5090-5053-6 | 3 |
PageRank | References | Authors |
0.48 | 3 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Toro-Frias | 1 | 17 | 3.59 |
| P. Martín-Lloret | 2 | 15 | 4.01 |
| R. Castro-López | 3 | 79 | 18.20 |
| Elisenda Roca | 4 | 129 | 26.84 |
| Francisco V. Fernández | 5 | 234 | 40.82 |
| Javier Martín-Martínez | 6 | 48 | 13.91 |
| R. Rodríguez | 7 | 36 | 11.51 |
| Montserrat Nafría | 8 | 23 | 5.27 |