Name
Title | ||
|---|---|---|
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging |
Abstract | ||
|---|---|---|
In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/SMACD.2017.7981600 | 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) |
Keywords | Field | DocType |
Bias Temperature Instability (BTI),Random Telegraph Noise (RTN),Channel Hot Carriers (CHC),variability,aging,degradation | Transistor array,Chip,CMOS,Electronic engineering,Electrical testing,Engineering,Process variability,Transistor,Electrical engineering,Temperature measurement | Conference |
ISSN | ISBN | Citations |
2575-4874 | 978-1-5090-5053-6 | 3 |
PageRank | References | Authors |
0.64 | 3 | 10 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Diaz-Fortuny | 1 | 5 | 1.25 |
| Javier Martín-Martínez | 2 | 48 | 13.91 |
| R. Rodríguez | 3 | 36 | 11.51 |
| Montserrat Nafría | 4 | 23 | 5.27 |
| R. Castro-López | 5 | 79 | 18.20 |
| Elisenda Roca | 6 | 129 | 26.84 |
| Francisco V. Fernández | 7 | 234 | 40.82 |
| Enrique Barajas | 8 | 6 | 4.27 |
| xavier aragones cervera | 9 | 45 | 9.62 |
| Diego Mateo | 10 | 43 | 10.97 |