Name
Title | ||
|---|---|---|
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications |
Abstract | ||
|---|---|---|
We have developed 3rd generation DRP, dynamically reconfigurable processor, for accelerating deep neural networks (DNNs) in embedded micro-processor systems. A DRP unit (supporting 16b FP from this generation) and a newly designed multiply-and-accumulate (MAC) unit are tightly integrated into an STP-3 AI core to achieve high versatility, high performance, and low latency DNN processing. The core also features narrow bit-width streaming data exchange mechanism between the two units. Not only basic 16b FP but also binarized DNN inference computations are supported. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/VLSIC.2018.8502438 | 2018 IEEE Symposium on VLSI Circuits |
Keywords | Field | DocType |
multiply-and-accumulate unit,STP-3 AI core,low latency DNN processing,narrow bit-width streaming data exchange mechanism,new generation dynamically reconfigurable processor technology,3rd generation DRP,deep neural networks,embedded microprocessor systems,high performance processing,embedded AI applications,MAC unit,binarized DNN inference computations | Kernel (linear algebra),Computer architecture,System on a chip,Computer science,Inference,Convolution,Parallel computing,Acceleration,Latency (engineering),Computation,Applications of artificial intelligence | Conference |
ISSN | ISBN | Citations |
2158-5601 | 978-1-5386-4215-3 | 0 |
PageRank | References | Authors |
0.34 | 0 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taro Fujii | 1 | 33 | 4.81 |
| Takao Toi | 2 | 32 | 3.85 |
| Teruhito Tanaka | 3 | 0 | 0.34 |
| Katsumi Togawa | 4 | 2 | 1.16 |
| Toshiro Kitaoka | 5 | 18 | 2.17 |
| Kengo Nishino | 6 | 0 | 0.34 |
| Noritsugu Nakamura | 7 | 30 | 2.75 |
| Hiroki Nakahara | 8 | 155 | 37.34 |
| Masato Motomura | 9 | 91 | 27.81 |