Name
Abstract | ||
|---|---|---|
High-end embedded systems, like their general-purpose counterparts, are turning to many-core cluster-based shared-memory architectures that provide a shared memory abstraction subject to non-uniform memory access costs. In order to keep the cores and memory hierarchy simple, many-core embedded systems tend to employ simple, scratchpad-like memories, rather than hardware managed caches that require some form of cache coherence management. These “coherence-free” systems still require some means to synchronize memory accesses and guarantee memory consistency. Conventional lock-based approaches may be employed to accomplish the synchronization, but may lead to both usability and performance issues. Instead, speculative synchronization, such as hardware transactional memory, may be a more attractive approach. However, hardware speculative techniques traditionally rely on the underlying cache-coherence protocol to synchronize memory accesses among the cores. The lack of a cache-coherence protocol adds new challenges in the design of hardware speculative support. In this article, we present a new scheme for hardware transactional memory (HTM) support within a cluster-based, many-core embedded system that lacks an underlying cache-coherence protocol. We propose two alternative data versioning implementations for the HTM support, Full-Mirroring and Distributed Logging and we conduct a performance comparison between them. To the best of our knowledge, these are the first designs for speculative synchronization for this type of architecture. Through a set of benchmark experiments using our simulation platform, we show that our designs can achieve significant performance improvements over traditional lock-based schemes. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1007/s10766-018-0569-7 | International Journal of Parallel Programming |
Keywords | Field | DocType |
Transactional memory, Embedded systems, Parallel processing, Coherence-free memory architectures | Synchronization,Memory hierarchy,Shared memory,Lock (computer science),Computer science,Usability,Parallel computing,Transactional memory,Embedded system,Cache coherence,Software versioning | Journal |
Volume | Issue | ISSN |
46 | 6 | 0885-7458 |
Citations | PageRank | References |
0 | 0.34 | 13 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dimitra Papagiannopoulou | 1 | 26 | 3.62 |
| Andrea Marongiu | 2 | 337 | 39.19 |
| Tali Moreshet | 3 | 98 | 9.81 |
| Luca Benini | 4 | 13116 | 1188.49 |
| Maurice Herlihy | 5 | 8623 | 920.94 |
| R. Iris Bahar | 6 | 878 | 84.31 |