Name
Title | ||
|---|---|---|
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST |
Abstract | ||
|---|---|---|
Multi-cycle Test applies more than one capture cycles during the capture operation which is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power-on Self-Test) for achieving high fault coverage. However, the randomness loss of the capture patterns due to the large number of capture cycles obstructs the further improvement of fault coverage and pattern reduction. In this paper, we propose a novel approach to control the capture patterns by modifying the captured values of scan Flip-Flops (FFs) during capture operation to enhance the test quality of the capture patterns. In the approach, we insert FF-Control circuits between the scan FFs and the combinational circuit to improve the randomness of the capture patterns by loading toggle vectors/pseudo-random vectors. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction for Logic-BIST. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ATS.2018.00038 | 2018 IEEE 27th Asian Test Symposium (ATS) |
Keywords | Field | DocType |
BIST,Multi-Cycle Test,Fault Detection Degradation,FF Selection,POST | Fault coverage,Random pattern,Computer science,Fault detection and isolation,Test quality,Degradation Problem,Real-time computing,Combinational logic,Electronic circuit,Randomness | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-5386-9467-1 | 0 |
PageRank | References | Authors |
0.34 | 7 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Senling Wang | 1 | 18 | 5.91 |
| Tomoki Aono | 2 | 0 | 0.34 |
| Yoshinobu Higami | 3 | 140 | 27.24 |
| Hiroshi Takahashi | 4 | 148 | 24.32 |
| Hiroyuki Iwata | 5 | 7 | 2.92 |
| Yoichi Maeda | 6 | 13 | 5.96 |
| Jun Matsushima | 7 | 13 | 4.09 |