Name
Abstract | ||
|---|---|---|
Energy-constrained neural network processing is in high demanded for various mobile applications. Binary neural network aggressively enhances the computational efficiency, and in contrast, it suffers from degradation of accuracy due to its extreme approximation. We propose a novel accurate neural network model based on binarization and "dithering" that distributes the quantization error to neighboring pixels. The quantization errors in the binarization are distributed in the plane, so that a pixel in the multi-level source expression more accurately represented in the resulting binarized plane by multiple pixels. We designed a low-overhead binary-based hardware architecture for the proposed model. The evaluation results show that this method can be realized with a few additional lightweight hardware components. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/FPT.2018.00013 | 2018 International Conference on Field-Programmable Technology (FPT) |
Keywords | Field | DocType |
neural network, binary neural network, quantized neural network, approximate neural network, dithering, error diffusion, FPGA, hardware oriented algorithm | Computer science,Field-programmable gate array,Pixel,Low bit,Dither,Quantization (signal processing),Computer hardware,Artificial neural network,Hardware architecture,Binary number | Conference |
ISBN | Citations | PageRank |
978-1-7281-0215-3 | 1 | 0.43 |
References | Authors | |
1 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kota Ando | 1 | 24 | 6.81 |
| Kodai Ueyoshi | 2 | 22 | 3.84 |
| Yuka Oba | 3 | 3 | 2.82 |
| Kazutoshi Hirose | 4 | 5 | 2.94 |
| Ryota Uematsu | 5 | 1 | 1.79 |
| Takumi Kudo | 6 | 1 | 0.77 |
| M. Ikebe | 7 | 47 | 13.63 |
| Tetsuya Asai | 8 | 79 | 26.75 |
| Shinya Takamaeda-Yamazaki | 9 | 65 | 16.83 |
| Masato Motomura | 10 | 91 | 27.81 |