Name
Title | ||
|---|---|---|
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS |
Abstract | ||
|---|---|---|
A single channel 1.5GS/s 8-bit pipelined-SAR ADC utilizes a novel output level shifting (OLS) settling technique to reduce the power and enable low-voltage operation of the dynamic residue amplifier. The ADC consists of a 4-bit first stage and a 5-bit second stage, with 1-bit redundancy to relax the offset, gain, and settling requirements of the first stage. Employing the OLS technique allows for an inter-stage gain of ~4 from the dynamic residue amplifier with a settling time that is only 28% of a conventional CML amplifier. The ADC's conversion speed is further improved with the use of parallel comparators in the two asynchronous stages. Fabricated in a 14nm FinFET technology, the ADC occupies 0.0013mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
core area and operates with a 0.8V supply. 6.6-bit ENOB is achieved at Nyquist while consuming 2.4mW, resulting in an FOM of 16.7fJ/conv.-step. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/CICC48029.2020.9075942 | 2020 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | DocType | ISSN |
Analog-to-digital converter (ADC),output level shifting (OLS),pipelined-SAR | Conference | 0886-5930 |
ISBN | Citations | PageRank |
978-1-7281-6032-0 | 2 | 0.51 |
References | Authors | |
3 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuanming Zhu | 1 | 2 | 0.51 |
| Shengchang Cai | 2 | 20 | 5.28 |
| Shiva Kiran | 3 | 12 | 2.71 |
| Yang-Hang Fan | 4 | 2 | 0.51 |
| Po-Hsuan Chang | 5 | 2 | 0.51 |
| Sebastian Hoyos | 6 | 234 | 29.24 |
| Samuel Palermo | 7 | 142 | 22.07 |