Paper Info
Title
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS
Abstract
Low-clock-power digital standard cell IPs in 10nm CMOS, featuring low-power shared-clock (LPSC) flip-flops (FFs), LPSC back-to-back (B2B) FFs, and pass-gate (PG) integrated clock gates (ICGs), achieve up to 14%, 45%, and 14% measured clock energy improvements, respectively, by reducing the number of clocked devices over state-of-the-art conventional transmission-gate (TG) FF and AND ICG circuits. The LPSC FF achieves a mean worst-case black-hole-time (BHT) improvement of 17ps, while the PG ICG achieves a mean enable/disable setup time improvement of 16ps/15ps, compared to conventional circuits measured at 650mV, 25°C. Power analysis of a graphics processor block with these optimized IPs results in an overall 6% clock power reduction without frequency impact.
Year
DOI
Venue
2020
10.1109/VLSICircuits18222.2020.9163007
2020 IEEE Symposium on VLSI Circuits
Keywords
DocType
ISSN
CMOS,low-clock-power digital standard cell IPs,low-power shared-clock,clocked devices,worst-case black-hole-time improvement,clock power reduction,measured clock energy improvements,low-clock-power digital standard cell IP,high-performance graphics,AI processors,flip-flops,LPSC back-to-back FF,pass-gate,integrated clock gates,transmission-gate FF,AND ICG circuits,mean enable-disable setup time improvement,power analysis,graphics processor block,temperature 25.0 degC,size 10.0 nm,time 16.0 ps,time 15.0 ps,voltage 650.0 mV
Conference
2158-5601
ISBN
Citations 
PageRank 
978-1-7281-9943-6
0
0.34
References 
Authors
0
16
Name
Order
Citations
PageRank
S. K. Hsu152152.06
Amit Agarwal269372.95
Simeon Realov3262.92
Mark A. Anders418517.43
Gregory K. Chen529832.96
Monodeep Kar65312.66
Raghavan Kumar77312.56
Huseyin Sumbul862.29
Phil Knag9183.17
Himanshu Kaul1045651.07
Vikram B. Suresh113110.23
S. Mathew1246276.59
Iqbal Rajwani1300.34
Satish Damaraju14405.40
Ram Krishnamurthy1565074.63
Vivek De163024577.83