Name
Title | ||
|---|---|---|
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm |
Abstract | ||
|---|---|---|
We present Versa, an energy-efficient processor with 36 systolic ARM Cortex-M4F cores and a runtime-reconfigurable memory hierarchy. Versa exploits algorithm-specific characteristics in order to optimize bandwidth, access latency, and data reuse. Measured on a set of kernels with diverse data access, control, and synchronization characteristics, reconfiguration between different Versa modes yields median energy-efficiency improvements of 11.6× and 37.2× over mobile CPU and GPU baselines, respectively. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.23919/VLSICircuits52068.2021.9492391 | 2021 Symposium on VLSI Circuits |
Keywords | DocType | ISSN |
GPU,CPU,synchronization characteristics,diverse data access,data reuse,access latency,algorithm-specific characteristics,systolic ARM Cortex-M4F cores,Versa,median energy-efficiency improvements,runtime-reconfigurable memory hierarchy,energy-efficient processor,reconfigurable crossbar-memory hierarchy,dataflow-centric multiprocessor,size 28 nm | Conference | 2158-5601 |
ISBN | Citations | PageRank |
978-1-6654-4766-9 | 1 | 0.35 |
References | Authors | |
0 | 13 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sung Kim | 1 | 1 | 0.35 |
| Morteza Fayazi | 2 | 1 | 0.69 |
| Alhad Daftardar | 3 | 1 | 0.35 |
| Kuan-Yu Chen | 4 | 1 | 0.35 |
| Jielun Tan | 5 | 3 | 2.41 |
| subhankar pal | 6 | 32 | 5.27 |
| Tutu Ajayi | 7 | 20 | 3.28 |
| Yan Xiong | 8 | 5 | 0.76 |
| Trevor Mudge | 9 | 6139 | 659.74 |
| Chaitali Chakrabarti | 10 | 1978 | 184.17 |
| David T. Blaauw | 11 | 1 | 1.02 |
| Ronald G. Dreslinski | 12 | 1258 | 81.02 |
| Hun-Seok Kim | 13 | 294 | 27.15 |