Author Info
Name
Affiliation
Papers
THIERRY BONNOIT
Laboratoire TIMA, Grenoble Cedex, France 38031
6
Collaborators
Citations 
PageRank 
5
6
2.27
Referers 
Referees 
References 
22
87
29
Title
Citations
PageRank
Year
Designing Reliable Processor Cores In Ultimate Cmos And Beyond: A Double Sampling Solution00.342018
Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance.00.342018
Low cost rollback to improve fault-tolerance in VLSI circuits00.342017
SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core20.452017
Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study30.442013
Towards a tool for implementing delay-free ECC in embedded memories10.362011