Kwang-jow Gan - Citegraph

Author Info

Name	Affiliation	Papers
KWANG-JOW GAN	Kun Shan Univ, Dept Elect Engn, Yung Kang, Tainan County, Taiwan	13
Collaborators	Citations	PageRank
22	10	5.16
Referers	Referees	References
21	42	21

Publications (13 rows)

Collaborators (22 rows)

Referers (21 rows)

Referees (42 rows)

Title	Citations	PageRank	Year
The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET.	0	0.34	2013
Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process	2	0.43	2011
Investigation Of Adjustable Current-Voltage Characteristics And Hysteresis Phenomena For Multiple-Peak Negative Differential Resistance Circuit	0	0.34	2010
Novel Multiple-Valued Logic Design Using Bicmos-Based Negative Differential Resistance Circuit Biased By Two Current Sources	0	0.34	2010
Standard Bicmos Implementation Of A Two-Peak Negative Differential Resistance Circuit With High And Adjustable Peak-To-Valley Current Ratio	1	0.41	2009
Multiple-Valued Memory Design by Standard BiCMOS Technique	0	0.34	2009
New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits	1	0.40	2008
The Design of MOS-BJT-NDR-Based Cellular Neural Network	0	0.34	2006
Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process	1	0.40	2006
Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process	1	0.40	2006
Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits	1	0.48	2005
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits	2	0.58	2005
Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process	1	0.38	2005

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