Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. | 0 | 0.34 | 2021 |
Benchmarking Flaws Undermine Security Research. | 0 | 0.34 | 2020 |
seL4 in Australia: from research to real-world trustworthy systems | 0 | 0.34 | 2020 |
Towards Provable Timing-Channel Prevention | 0 | 0.34 | 2020 |
Can We Prove Time Protection? | 0 | 0.34 | 2019 |
Fault Tolerance Through Redundant Execution on COTS Multicores: Exploring Trade-Offs | 0 | 0.34 | 2019 |
SoK: Benchmarking Flaws in Systems Security | 1 | 0.35 | 2019 |
A Formal Approach to Constructing Secure Air Vehicle Software. | 4 | 0.57 | 2018 |
Formally verified software in the real world. | 4 | 0.43 | 2018 |
Roundtable: Machine Learning for Embedded Systems: Hype or Lasting Impact? | 0 | 0.34 | 2018 |
Benchmarking Crimes: An Emerging Threat in Systems Security. | 4 | 0.44 | 2018 |
For Safety's Sake: We Need a New Hardware-Software Contract! | 0 | 0.34 | 2018 |
Scheduling-context capabilities: a principled, light-weight operating-system mechanism for managing time | 4 | 0.39 | 2018 |
Time Protection: the Missing OS Abstraction. | 5 | 0.41 | 2018 |
A Survey of Microarchitectural Timing Attacks and Countermeasures on Contemporary Hardware. | 45 | 1.24 | 2018 |
The Cogent Case for Property-Based Testing. | 0 | 0.34 | 2017 |
Technical Perspective: Proving file systems meet expectations. | 0 | 0.34 | 2017 |
High-assurance timing analysis for a high-assurance real-time operating system. | 1 | 0.35 | 2017 |
L4 Microkernels: The Lessons from 20 Years of Research and Deployment. | 8 | 0.52 | 2016 |
Report on the Asia-Pacific Systems Workshop 2015 (APSys'15). | 0 | 0.34 | 2016 |
It's Time: OS Mechanisms for Enforcing Asymmetric Temporal Integrity. | 2 | 0.41 | 2016 |
An Evaluation of Coarse-Grained Locking for Multicore Microkernels. | 1 | 0.35 | 2016 |
Cogent: verifying high-assurance file system implementations | 19 | 0.74 | 2016 |
Do Hardware Cache Flushing Operations Actually Meet Our Expectations? | 0 | 0.34 | 2016 |
For a Microkernel, a Big Lock Is Fine | 3 | 0.40 | 2015 |
Last-Level Cache Side-Channel Attacks are Practical | 223 | 5.34 | 2015 |
Mapping the Intel Last-Level Cache. | 14 | 0.80 | 2015 |
The Last Mile: An Empirical Study of Timing Channels on seL4 | 28 | 0.93 | 2014 |
Unifying DVFS and offlining in mobile multicores | 18 | 0.82 | 2014 |
Comprehensive formal verification of an OS microkernel | 80 | 2.54 | 2014 |
Mobile multicores: use them or waste them | 14 | 0.68 | 2014 |
Trickle: Automated infeasible path detection using all minimal unsatisfiable subsets | 11 | 0.58 | 2014 |
File systems deserve verification too! | 10 | 0.54 | 2014 |
The systems hacker's guide to the galaxy energy usage in a modern smartphone | 39 | 1.49 | 2013 |
Sequoll: A framework for model checking binaries | 1 | 0.36 | 2013 |
The von Neumann architecture is due for retirement | 1 | 0.37 | 2013 |
RapiLog: reducing system complexity through verification | 7 | 0.49 | 2013 |
Code optimizations using formally verified properties | 1 | 0.35 | 2013 |
From L3 to seL4 what have we learnt in 20 years of L4 microkernels? | 42 | 1.27 | 2013 |
A Scalable Lock Manager for Multicores. | 11 | 0.57 | 2013 |
It's Time for Trustworthy Systems | 6 | 0.64 | 2012 |
Trustworthy Real-Time Systems. | 0 | 0.34 | 2012 |
Improving interrupt response time in a verifiable protected microkernel | 11 | 0.74 | 2012 |
To preempt or not to preempt, that is the question | 3 | 0.40 | 2012 |
Protected hard real-time: the next frontier | 3 | 0.40 | 2011 |
Hardware-supported virtualization on ARM | 37 | 1.81 | 2011 |
What if you could actually trust your kernel? | 6 | 0.49 | 2011 |
Timing Analysis of a Protected Operating System Kernel | 33 | 1.11 | 2011 |
Architecture optimisation with currawong | 1 | 0.48 | 2011 |
Improved device driver reliability through hardware verification reuse | 4 | 0.41 | 2011 |