Name
Title | ||
|---|---|---|
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. |
Abstract | ||
|---|---|---|
A sparse matrix-matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40-nm CMOS. The compute fabric consists of dedicated floating-point multiplication units, and general-purpose Arm Cortex-M0 and Cortex-M4 cores. The on-chip memory reconfigures scratchpad or cache, depending on the phase of the algorithm. The memory and comput... |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/JSSC.2019.2960480 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Sparse matrices,Sorting,Indexes,Computer architecture,System-on-chip,Bandwidth,Kernel | Journal | 55 |
Issue | ISSN | Citations |
4 | 0018-9200 | 2 |
PageRank | References | Authors |
0.37 | 0 | 18 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dong-Hyeon Park | 1 | 28 | 2.49 |
| subhankar pal | 2 | 32 | 5.27 |
| Siying Feng | 3 | 20 | 1.61 |
| Paul Gao | 4 | 16 | 2.41 |
| Jielun Tan | 5 | 3 | 2.41 |
| Austin Rovinski | 6 | 137 | 7.24 |
| Shaolin Xie | 7 | 2 | 0.37 |
| Chun Zhao | 8 | 27 | 7.67 |
| Aporva Amarnath | 9 | 39 | 5.18 |
| Timothy Wesley | 10 | 2 | 0.37 |
| Jonathan Beaumont | 11 | 36 | 2.85 |
| Kuan-Yu Chen | 12 | 450 | 55.78 |
| Chaitali Chakrabarti | 13 | 1978 | 184.17 |
| Michael Bedford Taylor | 14 | 1707 | 154.51 |
| Trevor Mudge | 15 | 6139 | 659.74 |
| David Blaauw | 16 | 8916 | 823.47 |
| Hun-Seok Kim | 17 | 294 | 27.15 |
| Ronald G. Dreslinski | 18 | 1258 | 81.02 |