Paper Info
Title
Effective Post-BIST Fault Diagnosis for Multiple Faults
Abstract
With the increasing complexity of LSI, built-in self test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore the authors propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. The fault diagnosis based on the compressed responses from BIST was called the post-BIST fault diagnosis (Takahashi et al., 2005, Takamatsu, 2005). The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 (Sato et al., 2005) benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, the feasibility of diagnosing the large circuits within the practical CPU times can be confirmed. The feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis was proven
Year
DOI
Venue
2006
10.1109/DFT.2006.24
Arlington, VA
Keywords
Field
DocType
effective post-bist fault diagnosis,success ratio,production test,fault diagnosis,post-bist fault diagnosis,multiple stuck-at fault,manufacturing test,high success ratio,proposed diagnosis method,multiple faults,large circuit,chip
Logic testing,Computer science,Production testing,Electronic engineering,Real-time computing,Self test,Electronic circuit,Reliability engineering,Built-in self-test
Conference
ISSN
ISBN
Citations 
1550-5774
0-7695-2706-X
1
PageRank 
References 
Authors
0.39
11
7
Name
Order
Citations
PageRank
Hiroshi Takahashi114824.32
Shuhei Kadoyama210.72
Yoshinobu Higami314027.24
Yuzo Takamatsu415027.40
Koji Yamazaki5278.41
Takashi Aikyo69311.46
Yasuo Sato7384.46