Name
Title | ||
|---|---|---|
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply] |
Abstract | ||
|---|---|---|
For original article see H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko and T. Sumi, ibid., vol.31, pp.1157-69 (Aug. 1996). I have read with a great interest the article by H. Suzuki et al. I am familiar with their work, and I found their approach interesting. The idea used to simplify the leading zero anticipator (LZA) I found innovative and an improvement over the one used in the IBM R... |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/4.551927 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Logic,Detectors,Counting circuits,Application specific integrated circuits,Algorithm design and analysis,Circuit synthesis,Delay,Tree data structures,Signal design,Asia | Journal | 32 |
Issue | ISSN | Citations |
2 | 0018-9200 | 4 |
PageRank | References | Authors |
1.10 | 1 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| V. Oklobdzija | 1 | 4 | 1.10 |
| H. Suzuki | 2 | 238 | 31.31 |
| H. Morinaka | 3 | 38 | 5.36 |
| H. Makino | 4 | 15 | 5.28 |
| Y. Nakase | 5 | 18 | 2.41 |
| K. Mashiko | 6 | 49 | 9.50 |
| T. Sumi | 7 | 4 | 1.10 |