A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm.

Paper Info

Title
A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm.

Year	DOI	Venue
2008	10.1109/ISSCC.2008.4523236	ISSCC
Keywords	Field	DocType
chip	Architecture,Computer science,Electronic engineering,NAND gate,Conventional memory,Throughput,Memory architecture,Performance improvement	Conference
Citations	PageRank	References
0	0.34	0
Authors
43

Authors (43 rows)

Cited by (0 rows)

References (0 rows)

Name	Order	Citations	PageRank
Raul Cernea	1	4	1.89
Long Pham	2	6	2.47
Farookh Moogat	3	7	2.10
Siu Lung Chan	4	4	1.89
Binh Le	5	8	2.58
Yan Li	6	399	95.68
Shouchang Tsao	7	9	10.52
Taiyuan Tseng	8	8	1.46
Khanh Nguyen	9	128	10.39
Jason Li	10	9	2.14
Jayson Hu	11	0	0.34
Jong Park	12	21	4.21
Cynthia Hsu	13	5	1.38
Fanglin Zhang	14	0	0.34
Teruhiko Kamei	15	12	3.70
Hiroaki Nasu	16	8	1.80
Phil Kliza	17	4	1.12
Khin Htoo	18	8	1.81
Jeffery Lutze	19	0	0.34
Yingda Dong	20	2	1.21
Masaaki Higashitani	21	50	19.79
Junhui Yang	22	0	1.35
Hung-Szu Lin	23	4	1.03
Vamshi Sakhamuri	24	0	0.34
Alan Li	25	84	4.60
Feng Pan	26	8	1.81
Sridhar Yadala	27	0	0.34
Subodh Taigor	28	0	0.34
Kishan Pradhan	29	0	0.34
James Lan	30	8	1.81
Jim Chan	31	40	3.26
Takumi Abe	32	0	0.34
Yasuyuki Fukuda	33	0	0.34
Hideo Mukai	34	0	0.34
Koichi Kawakami	35	0	0.68
Connie Liang	36	0	0.34
Tommy Ip	37	0	0.34
Shu-Fen Chang	38	0	0.68
Jaggi Lakshmipathi	39	0	0.34
Sharon Huynh	40	8	2.14
Dimitris Pantelakis	41	4	1.12
Mehrdad Mofidi	42	13	11.55
Khandker Quader	43	18	2.83