Name
Abstract | ||
|---|---|---|
Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed in [10]. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/VLSI.Design.2009.60 | VLSI Design |
Keywords | Field | DocType |
coupling capacitance,floating line,adjacent line,open fault,open faults,benchmark circuit,adjacent signal lines,open fault model,fault effect,defective line,nm ic,open fault macro,metals,logic gates,capacitance,benchmark testing,fault model,macros,integrated circuits | Logic gate,Capacitance,Coupling,Computer science,Voltage,Real-time computing,Electronic engineering,Transmission gate,Electronic circuit,Integrated circuit,Fault model | Conference |
ISSN | Citations | PageRank |
1063-9667 | 5 | 0.50 |
References | Authors | |
9 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Masaki Hashizume | 2 | 98 | 27.83 |
| Toshiyuki Tsutsumi | 3 | 59 | 7.28 |
| Koji Yamazaki | 4 | 27 | 8.41 |
| Takashi Aikyo | 5 | 93 | 11.46 |
| Yoshinobu Higami | 6 | 140 | 27.24 |
| Hiroshi Takahashi | 7 | 148 | 24.32 |
| Yuzo Takamatsu | 8 | 150 | 27.40 |