Paper Info
Title
8.1 a 4x4x2 homogeneous scalable 3d network-on-chip circuit with 326mflit/s 0.66pj/b robust and fault-tolerant asynchronous 3d links
Abstract
By shortening communication distance across dies, 3D technologies are a key to continued improvements in computing density. For 4G telecom baseband processing, specific computing units arranged in a regular network-on-chip (NoC) array provide power-efficient computation [1]. However, for advanced MIMO processing, more computing power is required when the number of antennas increases. This paper presents a homogeneous 3D circuit composed of regular tiles assembled using a 4x4x2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.
Year
DOI
Venue
2016
10.1109/ISSCC.2016.7417949
2016 IEEE International Solid-State Circuits Conference (ISSCC)
Keywords
Field
DocType
3D network-on-chip circuit,fault-tolerant asynchronous 3D links,communication distance,4G telecom baseband processing,NoC,MIMO processing,CMOS technology,TSV,Face2Back configuration,size 65 nm
Asynchronous communication,Baseband,Computer science,MIMO,Robustness (computer science),Electronic engineering,CMOS,Fault tolerance,Redundancy (engineering),Scalability
Conference
ISBN
Citations 
PageRank 
978-1-4673-9466-6
10
0.78
References 
Authors
5
14
Name
Order
Citations
PageRank
Pascal Vivet160653.09
Yvain Thonnart234932.39
Romain Lemaire3797.92
Edith Beigne453652.54
Christian Bernard5465.36
Florian Darve6322.18
Didier Lattard714418.68
Ivan Miro Panades8967.81
Cristiano Santos9608.44
Fabien Clermidy1079761.56
Séverine Cheramy11224.74
Frédéric Pétrot1229947.74
Eric Flamand1328714.07
J. Michailos14152.65