Name
Title | ||
|---|---|---|
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. |
Abstract | ||
|---|---|---|
A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/JSSC.2017.2778702 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Biological neural networks,Random access memory,Memory management,Neurons,System-on-chip,Parallel processing | System on a chip,Computer science,In-Memory Processing,Electronic engineering,Ternary operation,Chip,Memory management,Tera-,Computer hardware,Artificial neural network,Binary number | Journal |
Volume | Issue | ISSN |
53 | 4 | 0018-9200 |
Citations | PageRank | References |
15 | 0.85 | 0 |
Authors | ||
11 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kota Ando | 1 | 24 | 6.81 |
| Kodai Ueyoshi | 2 | 22 | 3.84 |
| Kentaro Orimo | 3 | 16 | 1.57 |
| Haruyoshi Yonekawa | 4 | 34 | 4.37 |
| Shimpei Sato | 5 | 43 | 13.03 |
| Hiroki Nakahara | 6 | 155 | 37.34 |
| Shinya Takamaeda-Yamazaki | 7 | 65 | 16.83 |
| M. Ikebe | 8 | 47 | 13.63 |
| Tetsuya Asai | 9 | 121 | 26.53 |
| Tadahiro Kuroda | 10 | 659 | 213.23 |
| Masato Motomura | 11 | 91 | 27.81 |