Name
Title | ||
|---|---|---|
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS |
Abstract | ||
|---|---|---|
The emergence of four-level pulse amplitude modulation (PAM-4) standards to increase data rates motivates the use of receiver front ends that utilize high-speed analog-to-digital converters (ADCs) followed by digital signal processing (DSP) to provide robust digital equalization. This paper presents an ADC-based PAM-4 receiver employing a 32-way time-interleaved, 2-bit/stage, 6-bit successive approximation register (SAR) ADC with a single capacitive reference digital-to-analog converter (DAC) and a digital equalizer consisting of a 12-tap feed-forward equalizer (FFE) and a two-tap decision-feedback equalizer (DFE). A new digital DFE architecture that reduces the complexity of a PAM-4 DFE to that of a binary non-return-to-zero (NRZ) DFE, while simultaneously nearly doubling the maximum achievable data rate, is presented. Partial analog equalization is provided in the receiver front end in the form of a programmable two-stage continuous-time linear equalizer (CTLE) and a three-tap FFE that is embedded in the ADC using a non-binary FFE DAC to improve the FFE coefficient coverage space. This partial analog equalization allows placement of the digital baud-rate clock and data recovery (CDR) system’s Mueller–Muller phase detector directly at the ADC output to avoid excessive loop delay. Fabricated in GP 65-nm CMOS, the receiver achieves 32-Gb/s operation at a bit error rate (BER) <
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-9}$ </tex-math></inline-formula>
with a 30-dB loss channel and 52-Gb/s operation at a BER <
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-6}$ </tex-math></inline-formula>
with a 31-dB loss channel without utilizing any transmit equalization. The complete ADC-based receiver achieves a 52-Gb/s power efficiency of 8.06 pJ/bit, including all the front end, ADC, and DSP power. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/JSSC.2018.2878850 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Decision feedback equalizers,Receivers,Multiplexing,Complexity theory,Delays | Digital signal processing,Comparator,Equalization (audio),Computer science,CMOS,Electronic engineering,Phase detector,Successive approximation ADC,Pulse-amplitude modulation,Bit error rate | Journal |
Volume | Issue | ISSN |
54 | 3 | 0018-9200 |
Citations | PageRank | References |
2 | 0.37 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shiva Kiran | 1 | 12 | 2.71 |
| Shengchang Cai | 2 | 20 | 5.28 |
| Ying Luo | 3 | 3 | 0.85 |
| Sebastian Hoyos | 4 | 234 | 29.24 |
| Samuel Palermo | 5 | 142 | 22.07 |