Alessandro Cabrini

Author Info

Name	Affiliation	Papers
ALESSANDRO CABRINI	Univ Pavia, Dept Elect, Via Palestro 3, I-27100 Pavia, Italy	30
Collaborators	Citations	PageRank
74	108	24.11
Referers	Referees	References
356	322	99

Search Limit

100356

Publications (30 rows)

Collaborators (74 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Enhanced Compensation for Voltage Regulators Based on Three-Stage CMOS Operational Amplifiers for Large Capacitive Loads	0	0.34	2020
Current Tracking Technique Enabling 1-Bit/Cell Storage in Ge-Rich Phase Change Memory.	0	0.34	2019
2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications	3	0.58	2019
Selector-Memory Device Voltage Compatibility Considerations in 1S1R Crosspoint Arrays	0	0.34	2019
A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications.	2	0.63	2018
A Variability-Aware Analysis and Design Guideline for Write and Read Operations in Crosspoint STT-MRAM Arrays	1	0.41	2018
A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications.	1	0.41	2017
Integrated charge pumps: a generalised method for power efficiency optimisation	3	0.43	2016
Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions	16	0.74	2014
A theoretical charge transfer scheme for efficiency optimization of integrated charge pumps	0	0.34	2014
Drift-driven investigation of phase distribution in phase-change memories	1	0.42	2014
Optimal programming with voltage-controlled temperature profile to reduce SET state distribution dispersion in PCM	1	0.43	2014
Leakage-resilient memory-based physical unclonable function using phase change material	3	0.41	2014
Automatic trimming procedure to enhance the accuracy of on-chip analog pulse generators	0	0.34	2013
High-drive capability buffer for highly variable resistive loads	0	0.34	2012
Current reference scheme for multilevel phase-change memory sensing.	3	0.82	2011
A Multi-Level-Cell Bipolar-Selected Phase-Change Memory.	43	9.53	2008
Temperature dependence of the programmed states in GST-based multilevel phase-change memories.	2	0.75	2008
Design Of Maximum-Efficiency Integrated Voltage Doubler	0	0.34	2007
Cancellation of Amplifier Offset and 1/f Noise: An Improved Chopper Stabilized Technique	5	0.81	2007
Voltage Gain Analysis of Integrated Fibonacci-Like Charge Pumps for Low Power Applications	7	1.28	2007
Impact Of Control Signal Non-Idealties On Two-Phase Charge Pumps	3	0.67	2007
High-Efficiency Regulated Charge Pump for Non-Volatile Memories	0	0.34	2006
Thermal regulator for IC temperature characterization using a microprobe station	1	0.36	2006
High-Efficiency CMOS Charge Pump	0	0.34	2006
On-Line Calibration Of Offset And Gain Mismatch In Time-Interleaved Adc Using A Sampled-Data Chaotic Bit-Stream	5	0.46	2006
Power efficiency evaluation in Dickson and voltage doubler charge pump topologies	4	0.53	2006
Impact Of Parasitic Elements On Cmos Charge Pumps: A Numerical Analysis	3	0.62	2006
Theoretical and experimental analysis of Dickson charge pump output resistance	1	0.43	2006
High input range sense comparator for multilevel Flash memories	0	0.34	2004