| Enhancing Information Security Courses With a Remotely Accessible Side-Channel Analysis Setup | 0 | 0.34 | 2022 |
| Side-channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware Security | 0 | 0.34 | 2021 |
| A Lightweight Implementation of Saber Resistant Against Side-Channel Attacks. | 0 | 0.34 | 2021 |
| Lightweight Implementation of the LowMC Block Cipher Protected Against Side-Channel Attacks | 0 | 0.34 | 2020 |
| Face-off between the CAESAR Lightweight Finalists: ACORN vs. Ascon. | 0 | 0.34 | 2019 |
| Vulnerability Analysis of a Soft Core Processor through Fine-grain Power Profiling. | 0 | 0.34 | 2019 |
| A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography. | 0 | 0.34 | 2019 |
| An Open-Source Platform for Evaluation of Hardware Implementations of Lightweight Authenticated Ciphers | 0 | 0.34 | 2019 |
| Face-off Between the CAESAR Lightweight Finalists: ACORN vs. Ascon | 0 | 0.34 | 2018 |
| Experimental Power and Performance Evaluation of CAESAR Hardware Finalists | 0 | 0.34 | 2018 |
| Comparison Of Cost Of Protection Against Differential Power Analysis Of Selected Authenticated Ciphers | 0 | 0.34 | 2018 |
| The CAESAR-API in the real world — Towards a fair evaluation of hardware CAESAR candidates | 1 | 0.48 | 2018 |
| Comparing The Cost Of Protecting Selected Lightweight Block Ciphers Against Differential Power Analysis In Low-Cost Fpgas | 0 | 0.34 | 2018 |
| Fixing the CLOC with Fine-grain Leakage Analysis. | 0 | 0.34 | 2018 |
| Improved Lightweight Implementations of CAESAR Authenticated Ciphers | 0 | 0.34 | 2018 |
| Side-channel resistant soft core processor for lightweight block ciphers | 0 | 0.34 | 2017 |
| Evaluation of the CAESAR hardware API for lightweight implementations | 2 | 0.55 | 2017 |
| Implementation of efficient SR-Latch PUF on FPGA and SoC devices. | 1 | 0.35 | 2017 |
| A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures | 1 | 0.37 | 2017 |
| A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption | 0 | 0.34 | 2017 |
| CAESAR Hardware API. | 0 | 0.34 | 2016 |
| Comparison of multi-purpose cores of Keccak and AES | 3 | 0.41 | 2015 |
| Efficient SR-Latch PUF. | 4 | 0.45 | 2015 |
| FPGA PUF Based on Programmable LUT Delays | 1 | 0.37 | 2013 |
| Glitch Detection in Hardware Implementations on FPGAs Using Delay Based Sampling Techniques | 2 | 0.38 | 2013 |
| Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs | 5 | 0.67 | 2011 |
| A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs | 12 | 0.71 | 2011 |
| Lightweight implementations of SHA-3 candidates on FPGAs | 7 | 0.72 | 2011 |
| Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs | 8 | 0.49 | 2011 |
| ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs | 29 | 2.40 | 2010 |
| Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic | 4 | 0.45 | 2010 |
| Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs | 16 | 0.72 | 2010 |
| DPA Resistant AES on FPGA Using Partial DDL | 14 | 0.69 | 2010 |
| Compact FPGA implementation of Camellia | 3 | 0.44 | 2009 |
| Lightweight Cryptography for FPGAs | 32 | 1.60 | 2009 |
| DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs | 7 | 0.62 | 2009 |
| Chai-Tea, Cryptographic Hardware Implementations of xTEA | 12 | 0.76 | 2008 |
| Cryptography on a Speck of Dust | 21 | 1.36 | 2007 |
| Energy comparison of AES and SHA-1 for ubiquitous computing | 56 | 3.17 | 2006 |
| Energy scalable universal hashing | 34 | 2.70 | 2005 |
| State of the art in ultra-low power public key cryptography for wireless sensor networks | 65 | 5.69 | 2005 |
| Public key cryptography in sensor networks—revisited | 90 | 5.17 | 2004 |
| DES auf FPGAs - Hochgeschwindigkeits-Architekturen für den Data Encryption Standard auf rekonfigurierbarer Hardware | 0 | 0.34 | 1999 |
