| Guest Editorial Introduction to the Special Section on the 2021 RFIC Symposium | 0 | 0.34 | 2022 |
| A 100 Gb/s DC-Coupled Optical Modulator Driver for 3D Photonic Electronic Wafer-Scale Packaging | 0 | 0.34 | 2020 |
| A 16–43 GHz low-noise amplifer with 2.5–4.0 dB noise figure | 1 | 0.48 | 2016 |
| A fully integrated 30GHz 16-QAM single-channel phased array transmitter with 5.9% EVM at 6dB back-off. | 0 | 0.34 | 2015 |
| Generalized Semi-Analytical Design Methodology of Class-E Outphasing Power Amplifier | 2 | 0.38 | 2014 |
| A Fully Integrated Ka-Band VSAT Down-Converter | 1 | 0.48 | 2013 |
| A fully integrated down-converter for Ka-band VSAT satellite reception. | 1 | 0.44 | 2012 |
| A 1.95 GHz Sub-1 dB NF, +40 dBm OIP3 WCDMA LNA Module. | 0 | 0.34 | 2012 |
| A 1.95GHz sub-1dB NF, +40dBm OIP3 WCDMA LNA with variable attenuation in SiGe:C BiCMOS | 1 | 0.41 | 2011 |
| Advanced transmitters for wireless infrastructure. | 0 | 0.34 | 2011 |
| A 65nm CMOS pulse-width-controlled driver with 8Vpp output voltage for switch-mode RF PAs up to 3.6GHz | 3 | 0.67 | 2011 |
| A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS | 10 | 0.95 | 2010 |
| Reconfigurable RF and data converters. | 0 | 0.34 | 2010 |
| A 1.2-V 10-μ W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2°C (3 Sigma ) From - 70°C to 125°C. | 0 | 0.34 | 2010 |
| A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off | 13 | 2.74 | 2009 |
| A low-voltage mobility-based frequency reference for crystal-less ULP radios. | 0 | 0.34 | 2008 |
| Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum). | 0 | 0.34 | 2008 |
| A 0.6-to-10GHz Receiver Front-End in 45nm CMOS. | 15 | 3.80 | 2008 |
| A WiMedia-Compliant UWB Transceiver in 65nm CMOS. | 14 | 1.91 | 2007 |
| A Broadband Receive Chain in 65nm CMOS | 5 | 1.01 | 2007 |
| Transceiver design for multiband OFDM UWB | 3 | 0.72 | 2006 |
| A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS | 14 | 2.58 | 2004 |
| Mismatch-based timing errors in current steering DACs | 12 | 2.33 | 2003 |
| A general analysis on the timing jitter in D/A converters | 11 | 3.38 | 2002 |
| Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design | 1 | 0.34 | 2001 |
| High density capacitance structures in submicron CMOS for low power RF application | 3 | 1.58 | 2001 |
| Data processing based on wave propagation | 0 | 0.34 | 1999 |
| Further extensions to Chua's explicit piecewise linear function descriptions | 4 | 0.77 | 1996 |
| A New Architecture for a Cyclic Algorithmic D/A Converter | 0 | 0.34 | 1995 |
| DARWIN: CMOS opamp synthesis by means of a genetic algorithm | 83 | 14.12 | 1995 |
| A High Performance Low Voltage Switched-Current Multiplier | 2 | 1.16 | 1995 |
| Darwin - Analog Circuit Synthesis Based On Genetic Algorithms | 10 | 1.22 | 1995 |
| A flexible topology selection program as part of an analog synthesis system | 10 | 1.42 | 1995 |
| On The Restrictions Of The Sensitivities In Single-Amplifier Biquadratic Active-Filters | 0 | 0.34 | 1995 |
| DC Testing of Analog Integrated Circuits with Piecewise Linear Approximation and Interval Analysis | 2 | 0.39 | 1993 |
