Elyse Rosenbaum - Citegraph

Author Info

Name	Affiliation	Papers
ELYSE ROSENBAUM	Department of Electrical & Computer Engineering and Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1308 W. Main St., Urbana, Illinois	28
Collaborators	Citations	PageRank
56	61	21.99
Referers	Referees	References
192	1800	777

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Publications (28 rows)

Collaborators (56 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology	0	0.34	2022
Neural Networks for Transient Modeling of Circuits : Invited Paper	0	0.34	2021
Sub-nanosecond Reverse Recovery Measurement for ESD Devices	0	0.34	2020
Analysis and Design of Integrated Voltage Regulators for Supply Noise Rejection During System-Level ESD	0	0.34	2020
Model-Augmented Conditional Mutual Information Estimation for Feature Selection.	0	0.34	2020
Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors	0	0.34	2019
Stochastic modeling of air electrostatic discharge parameters	1	0.48	2018
A Study of BER-Optimal ADC-Based Receiver for Serial Links.	4	0.49	2016
Compact distributed multi-finger MOSFET model for circuit-level ESD simulation.	1	0.48	2016
Full-Component Modeling and Simulation of Charged Device Model ESD.	3	0.36	2016
Improved GGSCR layout for overshoot reduction	0	0.34	2015
Moving Signals On And Off Chip	0	0.34	2009
A new compact model for external latchup	0	0.34	2009
A Compact, ESD-Protected, SiGe BiCMOS LNA for Ultra-Wideband Applications	7	0.86	2007
Comprehensive ESD protection for RF inputs	7	2.03	2005
Noise characterization of static CMOS gates	2	0.40	2004
Critical evaluation of SOI design guidelines	0	0.34	2004
Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation	0	0.34	2003
A critical look at design guidelines for SOI logic gates	1	0.40	2002
Comprehensive frequency-dependent substrate noise analysis using boundary element methods	4	1.03	2002
Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits	2	0.49	2001
Trap generation and breakdown processes in very thin gate oxides	2	1.69	2001
Interconnect Thermal Modeling For Accurate Simulation Of Circuit Timing And Reliability	12	3.62	2000
Substrate modeling and lumped substrate resistance extraction for CMOS ESD/latchup circuit simulation	0	0.34	1999
Interconnect thermal modeling for determining design limits on current density	2	1.90	1999
Hierarchical electromigration reliability diagnosis for VLSI interconnects	2	0.45	1996
ETS-A: a new electrothermal simulator for CMOS VLSI circuits	5	1.29	1996
ICET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips	6	1.97	1996